The topics to be cover in VERILOG

Abstract: This is just a glance on verilog like what are all the concepts in veriolg .You can  feel like the Blueprint of verilog index.

1. Verilog history.
2. Basic concepts.


1. Lexical Elements
1. white spaces.
2. Comments.
3. Operators.
4. Number Specifications.
• Sized.
• Unsized.
• X and Z Values.
• Negative Numbers.
• Underscore & Question marks.
5. Strings.
6. Identifiers & Keywords.
7. Escaped Identifiers.
2. Data Types.
1. Value Set{0,1,X,Z}.
2. Nets.
3. Registers.
4. Vectors.
5. Integers,Real&Time.
6. Arrays.
7. Memories.
8. Parameters.
9. Strings.
10. System Task & Compiler Directives.
1. System Task.
• $display.
• $monitor.
• $stop.
• $finish.
2. Compiler Directives.
• `define.
• `include.




3. Module and Ports.


1. Port.
2. Port Connection Rules.
3. Port Types.
• input.
• output.
• inout.
4. Connecting Ports to External Signals.
• Connecting by Order List.
• Connecting Ports by Name.
5. Gate Level Modeling.
1. {and,nand,or,nor,xor,xnor}.
2. {buf,not}.
3. {buif1,bufif0}.
6. Stimulus Block.




4. Data Modeling.


1. Continuous Assignment{assign a=b+c;}.
2. Regular Delay Assignment{#2 a=b+c;}.
3. Expressions,operators & precedence
4. === vs ==
5. Conditional Statement{ ?:T : F ;}.
6. Concatenation{ {} }.




5. Behavioral Modeling. 


1. Structured Procedures
• Initial Statements.
• Always Statements.
2. Procedural Assignments.
• Blocking.
• Non Blocking.
3. Timing Controls.
1. Delay Based.
• Regular/Inter/Inertial{#dealy_value a = b+c;}.
• Intra/Transport{a = #b+c;}.
• Zero Delay{#0 a=b+c;}.
2. Event -Based Timing Control.
• Regular Event{posedge,negedge}.
• Named Event{User defined event:Ex:after_2_posedge..etc}.
• Event or Controll{@(a or b or c),@(a,b,c)}.
3. Level Sensitive.
• wait.
4. Conditional Statements
1. If, If_Else,If_Else_If.
2. Multi-way Branching.
• case.
• casex.
• casez.
3. Loops.
• While.
• For Loop.
• Repeat{loop_terminating,loop_increment are implicitly defined }.
• Forever.
5. Sequential And Parallel Blocks.
1. Sequential
• begin    end.
2. Parallel 
• fork     join.
3. Special Features of Blocks.
• Nested Blocks
• Naming Blocks{important feature in generate statement}.
• Disabling Blocks.
6. Task and Functions.
1. Task{0<= execution_time <= Non_zero}.
2. Function {executes in Zero simulation time}.
3. Task vs Functions.
4. Try Parity Calculator{Logic:cal_par=^ address-bits}. 
5. Try Left/Right shift register{Logic shift=(control ==`Leftshift)?(address<<1):(address>>1)}Its like for one call of task/fun one bit shift.




6. Useful Modeling Techniques.


1. assign and  deassign{Forces only register values}.
2. force and release {Forces both register and net values}.
3. Over Riding Parameters.
• defparam.
• Module instance parameter.
4. Conditional Compilation & Execution.
1. Compilation.
• `if def
• `else
• `endif
2. Execution.
• $test$plusargs.
5. Time Scales
• `timescale.{`timescale time-unit/precision }.
6. Useful System Tasks.
1. File Open
1. Opening File{$fopen("file_name")}.
2. Writing to Files.
• $fdisplay {$fdisplay(file_pointer, formatted string );}
• $monitor{$fmonitor(file_pointer, formatted string );}.
• $fdisplay vs $fmonitor vs $fstorbe.{$fdisplay &$diasplay both are same in functionality but differ in output stream former one is to file and later one is to i/o terminal similarly $monitor,$strobe}.
3. Closing a file.
• $flcose{$fclose("file_pointer);}.
4. Random Number Generation.
• $random.
• $random(<seed>);
5. Initializing Memory file.
• $readmemory(<"file_name">,<"memory_name">).
6. VCD{Value change Dump}.




7. Timing Delays.


1. Types of delay models.
• Distributed.
• Lumped.
• pin-to-pin delay.
2. Path delay modeling.
1. Specify Block
2. Inside Specify Block.
• Parallel Connection.
• Full Connection.
• Specparam statement.
• Conditional Path delays.
• Rise,fall and turnoff delays.
• min,typical,max delays.
3. Timing Checks.
1. $setup{$steup(ref_event,data_eent,limit,notifier);}
2. $hold{$hold(data_eent,ref_event,limit,notifier);}.
3. $width{$width(data_event,limit);}.
4. $period{$period(ref_event,period_limit);}.
5. $skew{$skew(ref_event,data-_event,skew_limit,notifier);}.




8. User Defined Udp's.


1. Udp Basics
• Udp_name {primitive Name_of_udep}.
• Terminal Declarations{input,output,reg} .
• Initialization{initial <output_terminal>=value}.
• State_table.




9. Udp Rules.


• Only scalar input terminals{1 bit}.
• Only one output terminal{1 bit}.
• Z is not handled by Udp.
•  inout ports are not supported.
1. Combinational Udps.
1. with out initialization_bock,register_values..etc.
2. Sequential Udps.




10. Miscellaneous Topics.


1.  Verilog 95 vs Verilog2001{in terms of features provided additionally }.
2. What is Latchup.
3. Parameter vs Local-parameter.
4. Synthesizable Code.
5. Try to write code FF,MUX,SHIFT_REG, using only single assignment statement.
6. Memories{synchronous and asynchronous }.
• Single port.
• Dual port.
• EeepRom.
7. State Diagrams in verilog.
• Sequence recognizer.
8. Full_case & Parallel_case foe case statement.
9. Generate Statement
Conclusion : All the  topic are listed and once again i am reminding these are only topics no explanation is provided for present . it will be included in soon Any suggestions make it as comment 

Welcome Message

Hi friends.

This is blog on vlsi cocepts.

This is new blog and i am also new to blogging but not vlsi ofcourse

Any subject i will start with posting of  complete  index which is useful to check topics to be covered in that subject.

Later on you can see valuable posts  on the subject.

Based on Index itself Users can post you doubts.

In soon material,Textbook solution Manuals will be updated.

Thats  it this is my first post to this blog .